In-Orbit Validation of a Heterogeneous COTS Architecture for Onboard AI: System-Level Operational Vulnerabilities and Failure Pathways

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초록

The adoption of Commercial-Off-The-Shelf (COTS) processors for in-orbit AI is limited by operational reliability risks with limited in-orbit data. This paper reports an in-orbit validation of a heterogeneous architecture combining a Microchip PolarFire SoC and an NVIDIA Jetson Orin NX. In this on-orbit dataset, many observed faults stem from system integration and operational protocol-driven degradation rather than from isolated radiation events. The PolarFire-based system instability aligned with a fragile I/O boot chain at the storage interface rather than the SoC silicon. The Jetson-based system exhibited an end-of-life cascade consistent with cumulative storage degradation under repeated abrupt power cycles. In this paper, the term vulnerability refers to operational reliability failure modes rather than cyber-security exploits. This paper does not assess cyber-security vulnerabilities in open-source or COTS software. The results support a heterogeneous architecture where a resilient Supervisory Node manages recovery actions for a high-performance accelerator.

키워드

Onboard computing; COTS; Heterogeneous; Architecture; System-Level; Vulnerability; In-Orbit Demonstration; NVIDIA Jetson
제목
In-Orbit Validation of a Heterogeneous COTS Architecture for Onboard AI: System-Level Operational Vulnerabilities and Failure Pathways
저자
원동식; 홍경우; 이동우; 이헌철; 방효충
DOI
10.1007/s42405-026-01130-w
발행일
2026-07
유형
Article
저널명
International Journal of Aeronautical and Space Sciences
권
27
호
4
페이지
3642 ~ 3659